1. Field of the Invention
The present invention relates in general to integrated circuit (IC) wafer testers and in particular to a system for calibrating signal timing of IC wafer tester channels to compensate for variation in signal paths between the tester and test probe points on a calibration wafer.
2. Description of Related Art
Integrated circuits (ICs) are usually fabricated in the form of die on a semiconductor wafer, and the die may thereafter be separated from one another and packaged. To avoid the cost of packaging defective ICs it is advantageous to test the ICs while they are still wafer form. An integrated circuit tester tests an IC by sending a sequence of test signals to its input terminals and monitoring the output signals produced by the IC to determine whether they behave as expected. A typical integrated circuit tester includes a xe2x80x9ctest headxe2x80x9d containing circuit boards implementing a set of tester channels. Each tester channel is capable of supplying a test signal input to an IC input/output (I/O) terminal or of monitoring an IC output signal produced at that I/O terminal. A tester also includes an interconnect system to link each tester channel to an appropriate I/O terminal of a die on the wafer under test. For example an interconnect system may include a xe2x80x9cprobe cardxe2x80x9d having an upper surface including contact points for receiving tips of pogo pins extending downward from the test head for conveying signals between the channels in the test head and the probe card. A set of probes on an undersurface of the probe card are arranged to contact pads or other types of contact points on the surface of the IC die that act as the IC""s I/O terminals. The probe card also includes vias and other conductors for interconnecting the probes and the pogo pin contacts. Since the product of the number of I/O terminals on a die and the number of die on a wafer usually exceeds the number of available channels on a tester, the tester usually tests part of the wafer per probe touchdown, sometimes only one die. A xe2x80x9cproberxe2x80x9d that holds the wafer while being tested positions the particular set of die to be tested under the probes and brings the wafer into contact with the probe tips during testing. After each test is completed the prober repositions (steps) the wafer so that the probes access a next set of die to be tested.
To properly test an IC, a tester must coordinate the timing of the activities of its channels. When a first tester channel changes the state of an IC input signal at some IC input terminal, we might expect a second tester channel to observe a particular state change in an IC output signal appearing at some IC output terminals a specific time thereafter. We consider an IC to be defective when an appropriate IC output signal state change does not occur with the correct delay following an IC input signal state change. Thus the tester must closely coordinate the time at which the first tester channel changes the input signal state with the time at which the second tester channel samples the IC output signal to determine its state.
An IC tester coordinates the timing of test events by supplying a periodic master clock signal concurrently to all of its channels. The channels time their activities with reference to the timing of edges of that master clock signal. However merely supplying the same master clock signal to all channels is not sufficient to ensure that they will precisely coordinate timing of events. One reason for this is that since the channels reside in separate locations within the test head, the master clock signal must travel from its source to each channel by a separate signal path, and differences in the lengths or electrical characteristics of each clock signal path can cause the clock signal edges to arrive at the channels at different times. Differences in timing can also arise from differences between channels. While tester channels may be made of integrated circuits of identical design, due to process variations no two ICs are exactly alike and one IC may process signals slightly faster than another. Also since the channels reside in separate locations within the test head, they may operate in differing temperature environments or may be subject to differing levels of stray capacitance or other environmental factors that influence the speed with which signals pass through internal circuits and conductors within each channel. Variations in the lengths or impedance characteristics of signal paths through the interconnect system linking the tester channels to the wafer also cause timing variations between the channels.
To provide more precise timing coordination, it is necessary calibrate the timing of each channel to greatly reduce the timing variations caused by such factors. For example a tester channel typically includes a timing signal generator for producing a set of timing signals that are of varying phase relative to the master clock signal. The timing signals control the timing of various test events such as the state changes in the test signal sent to the DUT or the sampling of DUT output signals. Some testers provide a mechanism for separately retarding or advancing the phase of the timing signals of each channel relative to the master clock signal to compensate for timing differences between channels. Other testers employ other mechanisms for separately adjusting each channel""s timing relative to the master clock signal.
To make use of such timing calibration systems it is necessary to separately measure the timing of each channel to determine whether to retard or advance the timing of the channel""s activities relative to the master clock signal. Typically the timing of state changes in a test signal produced at each channel I/O terminal (e.g. pogo pin) is compared to the timing of state changes of the master clock signal. The relative phase of the timing signals produced by each channel can then be iteratively adjusted so that the state change in its output test signal occurs on an edge of the master clock signal. This ensures that all channels have the same relative timing with respect to events at the tips of the pogo pins.
Although the measurement of event timing at the pogo pin tips rather than at the probe tips that contact the device under test does not account for differences in the signal paths provided by the interconnect system linking the channel I/O terminals to wafer test points, the measurement is carried out at the pogo pins, rather than at the probe tips for several reasons. First, it is much easier for test equipment to access the pogo pins than the probe tips because the pogo pins are much larger and more widely spaced. Secondly, since different wafers require different interconnect systems, it would be necessary to re-calibrate the system whenever a new interconnect system is required. Finally, and perhaps most importantly, the relatively small timing skew caused by interconnect system signal path differences can often be ignored.
However as the operating frequency of ICs has continued to increase, the resolution with which events must be timed has also increased to the point where even small variations in signal paths through the interconnect system can no longer be ignored. Therefore what is needed is a system for easily measuring timing differences between channels at the tips of the probes that contact the wafer.
Another factor associated with the paths that interconnect tester channels to a wafer can adversely affect the ability of a tester to test a high frequency IC. All signal paths attenuate signals, and the amount of signal attenuation depends not just on the path resistance but also on its frequency responsexe2x80x94a function of the path""s resistance, capacitance and inductance. Signal paths generally attenuate higher frequency signals more than lower frequency signals. A signal path having a relatively low frequency response can attenuate a high frequency IC input or output signal so much that it will change its apparent state when it arrives at its destination. Thus as IC signal frequencies continue to increase, test engineers have begun to pay more attention to the frequency response of the interconnect paths to make sure they don""t attenuate high frequency signals too much.
However the frequency response of an interconnect system signal path may not be what a test engineer expects it to be. Frequency response can vary, for example, due to errors in fabrication, distortion or contamination of probes or other system components, or environmental influences. When the frequency response of an interconnect path is not what it should be, states of high frequency logic signals can be misinterpreted by the tester or by the IC under test, and otherwise healthy ICs can fail tests.
Hence what is also needed is a system for easily measuring the frequency response of the signal paths of the interconnect system.
The present invention relates to an integrated circuit tester for testing an integrated circuit (IC) while still in the form of a die on a semiconductor wafer. The tester includes a set of tester channels that are linked by paths through an interconnect system to input/output terminals (pads) of the IC. Each channel includes a driver circuit for selectively sending a test signal to the pad via the interconnect path. The drive circuit can change the state of the test signal following each edge of a clock signal with a delay that includes the sum of a xe2x80x9cprogrammable drivexe2x80x9d delay and an adjustable xe2x80x9cdrive calibrationxe2x80x9d delay. Each channel also includes a compare circuit that can receive any IC output signal produced at IC pad and determine the output signal""s state with a delay following each clock signal edge that includes the sum of a xe2x80x9cprogrammable comparexe2x80x9d delay and an adjustable xe2x80x9ccompare calibrationxe2x80x9d delay. The invention relates in particular to a method and apparatus for adjusting the drive and compare calibration delays of the tester channels so that their activities can be closely coordinated when the IC is being tested.
In accordance with a first aspect of the invention, the interconnect system is adapted to provide an additional path linking a spare tester channel to a point on the IC other than a pad.
In accordance with a second aspect of the invention, to calibrate the timing of each tester channel that is to access an IC pad, the interconnect system sequentially connects the tester channels and spare channel to a set of connector areas on a calibration wafer. Each interconnect area includes a pair of terminals connected by a conductive path for linking an interconnect path leading to one of the tester channels to be calibrated to an interconnect path leading to the spare tester channel. Each connector area therefore allows a separate tester channel to send a test signal to the spare tester channel or to receive a test signal from the spare tester channel.
In accordance with a third aspect of the invention, each tester channel to be calibrated is programmed to produce an edge in its output test signal following selected clock signal edges with the same programmable drive delay. Each tester channel is then linked to the spare channel via one of the interconnect arcas on the calibration wafer so that its output test signal edge is sent to the spare tester channel. The spare tester channel is programmed to repeatedly sample a test signal with a fixed delay after each of the selected CLOCK signal pulses. The drive calibration delay of each tester channel is iteratively adjusted until the spare channel samples the test signal as close as possible to its edge.
In accordance with a fourth aspect of the invention, after the drive calibration delay of each tester channel is adjusted, pairs of tester channels are linked through additional interconnect areas on the calibration wafer when accessed via the interconnect system. One tester channel of each pair then sends a test signal edge to the other tester channel of the pair with a known programmable delay. The other tester channel of the pair is programmed to sample the test signal with the same known programmable delay. The compare calibration delay of the other tester channel is then iteratively adjusted until it samples the teat signal as close as possible to the test signal edge. The roles of the two channels of each pair are then reversed and the process is repeated to adjust the compare calibration delay of the other tester channel.
The above-described system calibrates the drive and compare timing of the tester channels not with respect to events occurring at their I/O terminals, but with respect to events occurring at the tips of the probes that contact the IC pads during a test. Thus unlike prior art systems, the calibration system of the present invention calibrates timing to account for differences not just in the tester channels but also in the signal paths linking those tester channels to the ICs being tested. This permits testing of high frequency ICs where it is necessary to provide very precise control over timing of events at the IC terminals.
It is accordingly an object of the invention to provide a system for adjusting the drive and compare calibration delays of IC tester channels so that their test activates may be closely coordinated.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.